1. Field of the Invention
The present invention relates to a timing budget designing method in a design stage of an LSI, and more particularly, to a method that can design an LSI while suitably considering signal delays when logical blocks of the LSI are laid out.
2. Description of the Related Art
Conventionally, an LSI design is composed of a floor plan step of determining in which LSI portions logical blocks are laid out after building up a logic and dividing the logic into the logical blocks, a step of replacing the logical blocks laid out by the floor plan with elements such as transistors, etc., and a step of wiring the elements.
However, with the above described conventional designing method, at the time of a floor plan, layout of logical blocks is determined without examining whether or not signal delays occurring when a logic circuit is wired conform to predetermined specifications. Therefore, if the logic circuit is actually formed by replacing the logical blocks with elements, and the logical blocks are wired, signal delays do not conform to specifications in some cases.
Since the layout of logical blocks must be conventionally changed at this time, a procedural return is frequently made to the floor plan step so as to redo the operations. Remaking a floor plan in the operations redone frequently includes how to divide a logic into blocks.
As described above, with the conventional LSI designing methods, a redo frequently occurs, and a lot of time is required for design, and at the same time, a designer requires much labor, leading to an increase in design cost.
This is because operations are performed without considering any signal delays, and as a result, signal delays do not conform to specifications frequently when a logic circuit is actually arranged.
An object of the present invention is to provide a timing budget designing method that can lay out logical blocks while suitably considering signal delays in an initial stage of an LSI design.
A timing budget designing method is a method that advances an LSI design while evaluating a timing budget. This method comprises the steps of: designing a logic embedded into an LSI, and dividing the logic into logical blocks; setting a delay value between pins of a logical block, and building a signal delay model; displaying the set delay value for a designer along with an interconnection relationship among the logical blocks; and designing the logical block while considering the delay value.
According to the present invention, a timing budget designing method that advances an LSI design while considering the delay values of logical blocks is provided, so that it becomes possible to decrease the number of situations where a signal delay does not fall within a required time frame in an advanced stage of LSI design. Consequently, the number of times that operations must be redone in a design stage, and design cost can be reduced. As a result, an efficient LSI design can be implemented.